1. Field of the Invention
The present invention relates to CMOS image sensors, and more particularly, to a method for fabricating a CMOS image sensor which can decrease a darkcurrent generated in an interface of a photodiode region and a field region.
2. Discussion of the Related Art
Generally, an image sensor is a semiconductor device for converting an optical image into an electric signal. In the image sensors, there are charge coupled devices (CCD) and complementary metal oxide semiconductor (CMOS) image sensors.
The charge coupled device (CCD) is provided with a plurality of photodiodes (PD) arranged in a matrix each for converting an optical signal into an electric signal, a plurality of vertical charge coupled devices (VCCD) formed between each vertical photodiode arranged in a matrix for vertical transmission of electric charges generated from each photodiode, a horizontal charge coupled device (HCCD) for horizontal transmission of the electric charges transmitted by each of the vertical charge coupled devices (VCCD), and a sense amplifier (Sense Amp) for sensing and forwarding the horizontally transmitted electric charges.
However, the charge coupled device (CCD) has disadvantages of a complicated driving method, high power consumption, and a complicated fabrication process requiring a multi-phased photo process. In the charge coupled device (CCD), a control circuit, a signal processing circuit, an analog to digital (A/D) converter circuit, and so on cannot be easily integrated into a charge coupled device chip, thereby having the problem of difficulty in forming compact-size products.
Recently, the complementary metal oxide semiconductor (CMOS) image sensor has been considered to be the next generation image sensor that can resolve the problems and disadvantages of the charge coupled device (CCD). The CMOS image sensor is a device adopting a CMOS technology using the control circuit, the signal processing circuit, and so on as a peripheral circuit, so as to form MOS transistors in correspondence with the number of unit pixels on a semiconductor substrate, in order to sequentially detect the electric signals of each unit pixel by using a switching method, thereby representing an image.
Since the CMOS image sensor uses a CMOS fabrication technology, the CMOS image sensor is advantageous in that it has low power consumption and has a simple fabrication method through less photo process steps. In the CMOS image sensor, a control circuit, a signal processing circuit, an A/D converter circuit, and so on can be integrated into a CMOS image sensor chip, thereby enabling the product to be fabricated in a compact size. Accordingly, the CMOS image sensor is currently and extensively used in various applied technologies, such as digital still cameras and digital video cameras.
Meanwhile, in the CMOS image sensors, there are a 3T-type, a 4T-type, and a 5T-type according to the number of transistors, wherein the 3T-type CMOS image sensor is provided with one photodiode and three transistors, and the 4T-type CMOS image sensor is provided with one photodiode and four transistors. A layout of a unit pixel in the 4T-type CMOS image sensor will be described as follows.
FIG. 1 illustrates a diagram of an equivalent circuit for a related art 4T-type CMOS image sensor, and FIG. 2 illustrates a layout of a related art unit pixel of a 4T-type CMOS image sensor.
Referring to FIG. 1, the unit pixel 100 of the CMOS image sensor is provided with a photodiode 110 as a photoelectric conversion part, and four transistors. The four transistors are a transfer transistor 120, a reset transistor 130, a drive transistor 140, and a select transistor 150. Also, the unit pixel 100 at an output terminal OUT thereof has a load transistor 160 electrically connected thereto.
Of the unexplained reference symbols, FD denotes a floating diffusion region, Tx denotes a gate voltage of the transfer transistor 120, Rx denotes a gate voltage of the reset transistor 130, Dx denotes a gate voltage of the drive transistor 140, and Sx denotes a gate voltage of the select transistor 150.
As shown in FIG. 2, the unit pixel of the related art 4T-type CMOS image sensor has an active region 15 (a thick line) defined therein to form a device isolation film in a portion except the active region 15. Of the active region 15, a portion with a large width has one photodiode PD formed therein, and overlapped with rest of the active region 15, there are gate electrodes 123, 133, 143, 153 of the four transistors formed thereon. That is, the transfer transistor 120 is formed by the gate electrode 123, the reset transistor 130 is formed by the gate electrode 133, the drive transistor 140 is formed by the gate electrode 143, and the select transistor 150 is formed by the gate electrode 153. Herein, impurity ions are injected to the active region 15 of the respective transistors except portions under the gate electrodes 123, 133, 143, 153, thereby forming source/drain regions S/D of the respective transistors.
A method for fabricating a unit pixel of a related art CMOS image sensor will be described.
FIGS. 3A to 3C illustrate sections across a line I-I′ in FIG. 2 showing the steps of a method for fabricating a related art CMOS image sensor.
Referring to FIG. 3A, a p-type epitaxial layer 102 is grown on a p-type semiconductor substrate 101, and a device isolation film 121 is formed in a portion excluding the active region of the p-type epitaxial layer 102 by an STI (Shallow Trench Isolation) process or the like.
An insulating film and a conductive layer are formed on an entire surface of the p-type epitaxial layer 102, and the insulating film and the conductive layer are removed selectively therefrom, to form a gate insulating film 122, and a gate electrode 123. Then, after a photoresist film is coated on entire surface of the substrate, a first photoresist film pattern 124 is formed for defining a lightly doped drain region for an LDD structure in a drain region on one side of the gate electrode 123 by photolithography process. In this instance, the first photoresist pattern does not expose the gate electrode 123.
In this state, impurity ions (for an example, n-type impurity ions) are injected into the active region of the substrate lightly, to form a lightly doped impurity region 115 in the substrate for the LDD structure.
Referring to FIG. 3B, the first photoresist film pattern 124 is removed, a second photoresist film pattern 125 is formed on the substrate to expose the photodiode region only, and impurity ions (for an example, n-type impurity ions) are injected lightly into the photodiode region, to form the photodiode 103.
Referring to FIG. 3C, the second photoresist film pattern 125 is removed, and an insulating film is deposited on entire surface thereof, and subjected to anisotropic etching, to form spacers 126 at sidewalls of the gate electrode 123.
A third photoresist film pattern (not shown) is formed on entire surface of the substrate so as to expose the photodiode region, and p-type impurity ions are injected by using the third photoresist film pattern and the spacers 126 as a mask, to form a p-type impurity region p0 in a surface of the photodiode 103 region. The p-type impurity region p0 serves to decrease a darkcurrent generated in the vicinity of a surface of the photodiode region.
Then, the third photoresist film pattern is removed, a fourth photoresist film pattern (not shown) is formed to expose the lightly doped impurity region 115 in the drain region on one side of the gate electrode 123, and n-type impurity ions are injected into the lightly doped impurity region 115 heavily by using the fourth photoresist film pattern and the spacers 126 as a mask, to form a heavily doped impurity region 127 in the drain region of the gate electrode 123.
However, the related art method for fabricating a CMOS image sensor has the following problems.
At the time of the n-type impurity injection into the p-type epitaxial layer for forming the photodiode region, of course, the impurities are injected into the active region, but, because the impurities are injected even to the device isolation film adjacent to the active region on which the photodiode is to be formed for some extent, there is current leakage from an interface of the active region and the device isolation film.
That is, the impurity ion injection into the interface of the active region and the device isolation film causes defects at the epitaxial layer of the interface, to produce charge or hole carriers, to provide places for reunion of the charges and the holes, thereby increasing the leakage current from the photodiode.
Consequently, a darkcurrent is generated, in which electrons migrate from the photodiode to the floating diffusion region in a state without light at all, starting from various defects and dangling bonds distributed mostly in surfaces of the photodiodes, interfaces of the device isolation film and the n-type regions of the photodiode, interfaces of the device isolation film and the p-type impurity region of the photodiode, interfaces of the p-type impurity region and the n-type impurity region of the photodiode, and the p-type impurity region and the n-type impurity region of the photodiode, and leads a low illumination characteristic of the CMOS image sensor poor.
In the meantime, U.S. Pat. No. 6,462,365, with a title “ACTIVE PIXEL HAVING REDUCED DARK CURRENT IN AL CMOS IMAGE SENSOR”, discloses a method for suppressing increase of the darkcurrent caused by dangling bonds at a surface of the photodiode by forming a device isolation film and a transfer gate on a surface of the photodiode as a protection film.
However, this method also fails to disclose a method for suppressing increase of the darkcurrent by preventing the impurity ions from being injected into the interface of the device isolation film and the active region for the photodiode.